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10??25??????15:00-17:00????
10??26??????8:30???锌??????
10??27??????17:00???薪?????
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?缍�??18217468860
E-mail??WangYi@MEMSConsulting.com

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Day One ?????

1. Nanoscale IC design challenge

The important design challenges and issues in nanoscale digital integrated circuits

The behaviors of transistors and circuits under the influence of short channel effects

The effects of process variations and temperature on nanoscale transistors and circuits

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2. low power design techniques

The different sources of power consumption in active circuits and idle circuits

The state-of-the-art low power design techniques for reducing dynamic power consumption as well as leakage power consumption

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3. Power gating I—Fundamentals

Power gating is the most commonly used leakage power reduction technique in idle circuits. In this session, the concept of power gating is introduced. Different implementation styles of power gating are presented. A variety of design challenges for implementing power gating is examined. The methods to size sleep transistors for power-gated circuits are explored. Different techniques to reduce the sizes of sleep transistors are introduced.

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4. Power Gating II—Advanced topics

In order to solve the various design issues with power gating, several advanced topics for implementing power gating are presented in this session. First of all, the mode transition scheduling techniques are explained to reduce the mode transition noise, delay, and energy overhead of power-gated circuits. Afterwards, how to implementing data retention in flip-flops and SRAM circuits are investigated. Finally, the tricks to implement power gating in back-end flow are introduced.

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Day Two ?????

5. Ultra-low voltage IC design

The energy profile of integrated circuits with voltage scaling is explored. The reasons why people would like to go to subthreshold region or near-threshold region for circuit operations are explained. The behavior of logic circuits in near-/sub-threshold regions is presented. The corresponding design challenges in ultra-low voltage regions are revealed. A new methodology for subthreshold standard cell library design is introduced.

The challenges of SRAM circuit design in ultra-low voltage region are introduced. Different techniques to facilitate ultra-low voltage SRAM circuit design are presented.

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6. Error-resilient circuit and system design

The influence of process, temperature, and voltage variations as well as aging and soft errors is so significant that designers have to leave large margins to deal with the worst-case scenario. The concept of “better-than-worst-case” design is introduced in this session. Different circuit techniques to deal with the timing violations under the influence of process, temperature, and voltage variations are explored. Furthermore, techniques to deal with the aging issues are investigated.

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Hailong Jiao

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Hailong Jiao????????????????????????????位???????????????????????????????????????????????????????????伪??????????芯?????IMEC?芯????????????芯??????????????????????VLSI??路??????????????????????????????????????????-??????????????????效??????????纭�??????????娲�????路??????????????????????????????璞�???璞�-??路协?????3D???????????????????????????????????????????????30??????????2???????????Elsevier Microelectronics Journal ??World Scientific Journal of Circuits, Systems, and Computers???????????????????????????????????????IEEE Asia and South Pacific Design Automation Conference (ASP-DAC 2016)??HiPEAC 2015 (MemTDAC: Memristor Technology, Design, Automation and Computing)??IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2014, 2015)??ACM/SIGDA Great Lakes Symposium on VLSI (GLSVLSI 2011)

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